Engineers at Harris Corporation are accustomed to delivering sophisticated FPGA-based signal processing systems within tight schedules. To meet their customers’ often stringent requirements and their own quality standards, the engineers thoroughly verify the HDL design of each system before it is synthesized.
In the past, HDL verification required several manual steps. Harris engineers have automated the process by using HDL Verifier™ to provide a bidirectional link between the MATLAB® system model and the HDL design simulated in Cadence® Incisive®. The new process eliminates ambiguity between the algorithm specification and HDL verification, reduces duplication of effort, and improves communication between system and HDL engineers.
“Cosimulation with MATLAB and HDL Verifier not only made it easier to simulate at the subsystem level, it also enabled us to verify the overall system more completely,” says Jason Plew, senior engineer at Harris. “We greatly reduced the time needed to develop subsystem test benches, which enabled us to verify and debug our designs much earlier.”