Sainath K, Design Engineer, NXP
Shashank Venugopal, Design Engineer, NXP
One of the key challenges offered by automotive radar designs is the functional and performance verification of signal processing hardware implementations like sigma delta ADCs, decimation chains, and filters. Verification of these signal processing blocks can be either done in time-domain or frequency domain. Time domain checks involve developing reference verification models, which are used to check the correctness of DUT implementation.
This methodology serves the basic requirement of checking functional correctness of DUT, but involves the development effort of reference models, which are highly sensitive to DUT design changes. Therefore, the team at NXP started looking at this problem to come up with a verification means using the powerful signal analysis functions of MATLAB®, and thereby, reducing the repetitive model development and increased verification productivity. The verification metrics used to evaluate the DUT implementation are FFT, SNR, and THD, which are computed using the built-in functions in MATLAB.
Shashank Venugopal presents the team’s experiences of integrating checks based on MATLAB into SV/UVM-based digital verification environments using DPI-C flow.
Recorded: 19 Apr 2018
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